3d chip stack
  • Integration from 300-mm wafers of monolithic 3D simple CMOS circuits with 14-nm node gates based on n-type InGaAs devices on top of p-type SiGe devices independently optimized.
  • Benchmark of InGaAs nFET with planar and non-planar Si based solutions at 14 nm and beyond nodes, with relevant critical dimensions.
  • Validation of InGaAs layer transfer for implementation on 300-mm wafers for mass production.
  • Understand the origin of Dit and explore possible origins of border traps at the interface between the InGaAs channel and the gate dielectric and its impact on transport properties.
  • Understanding the mechanism of source–drain contact formation on InGaAs and resultant resistance minimization.
  • Electrical evaluation at technologically relevant length scales backed up by quantitative analytic metrology to elucidate the science of low-resistance contact realization.
  • Demonstrate scalability of the InGaAs nFET integration process on FinFET on insulator architecture.
  • Channel the COMPOSE3 results as an extension of the FDSOI technology developed by STMicroelectronics.